library ieee;
use ieee.std_logic_1164.all;

entity mips_tb is
end mips_tb;

architecture behav of mips_tb is
    component mips is
        port(
        reset, clk, dump: in std_logic;
        instr, pc: out std_logic_vector(31 downto 0)
        );
    end component;

    signal reset_s, clk_s, dump_s: std_logic;
    signal instr_s, pc_s: std_logic_vector(31 downto 0);

begin
    Mips0: mips port map(reset_s, clk_s, dump_s, instr_s, pc_s);

    process -- Clock signal
        begin
        clk_s <= '1';
        wait for 1 ns;
        clk_s <= '0';
        wait for 1 ns;
    end process;

    process
    begin
        reset_s <= '1';
        wait for 2 ns;
        reset_s <= '0';
        wait for 36 ns;

        dump_s <= '1';
        wait;
    end process;
end behav;
